library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_3_8 is
    Port ( A    : in  STD_LOGIC_VECTOR (2 downto 0); -- 3-bit input
           EN_L : in  STD_LOGIC;                     -- Active-low enable
           Y    : out STD_LOGIC_VECTOR (7 downto 0)  -- 8-bit output
         );
end decoder_3_8;

architecture Dataflow of decoder_3_8 is
    signal EN : STD_LOGIC; -- Internal active-high enable
begin
    -- 1. Invert the active-low enable for internal use
    EN <= not EN_L;

    -- 2. Basic logic gate implementation for outputs
    Y(0) <= EN and (not A(2)) and (not A(1)) and (not A(0));
    Y(1) <= EN and (not A(2)) and (not A(1)) and      A(0) ;
    Y(2) <= EN and (not A(2)) and      A(1)  and (not A(0));
    Y(3) <= EN and (not A(2)) and      A(1)  and      A(0) ;
    Y(4) <= EN and      A(2)  and (not A(1)) and (not A(0));
    Y(5) <= EN and      A(2)  and (not A(1)) and      A(0) ;
    Y(6) <= EN and      A(2)  and      A(1)  and (not A(0));
    Y(7) <= EN and      A(2)  and      A(1)  and      A(0) ;

end Dataflow;