library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity decoder_3_8_TB is end decoder_3_8_TB; architecture Behavior of decoder_3_8_TB is component decoder_3_8 Port ( A : in STD_LOGIC_VECTOR (2 downto 0); EN_L : in STD_LOGIC; Y : out STD_LOGIC_VECTOR (7 downto 0)); end component; -- Signals to connect to the UUT (Unit Under Test) signal A_tb : STD_LOGIC_VECTOR (2 downto 0) := "000"; signal EN_L_tb : STD_LOGIC := '1'; signal Y_tb : STD_LOGIC_VECTOR (7 downto 0); function to_bstring(slv : std_logic_vector) return string is variable result : string(1 to slv'length); variable idx : integer := 1; begin for i in slv'range loop case slv(i) is when '0' => result(idx) := '0'; when '1' => result(idx) := '1'; when others => result(idx) := 'X'; end case; idx := idx + 1; end loop; return result; end function; begin UUT: decoder_3_8 Port map ( A => A_tb, EN_L => EN_L_tb, Y => Y_tb ); stim_proc: process variable i : integer; begin EN_L_tb <= '1'; A_tb <= "101"; wait for 10 ns; report "--- DECODER DISABLED ---"; report "EN_L=" & std_logic'image(EN_L_tb) & " Input A2,A1,A0= " & to_bstring(A_tb) & " | Output Y7...Y0= " & to_bstring(Y_tb) & LF & " "; wait for 10 ns; report "--- DECODER ENABLED ---"; EN_L_tb <= '0'; for i in 0 to 7 loop A_tb <= std_logic_vector(to_unsigned(i, 3)); wait for 10 ns; report "EN_L=" & std_logic'image(EN_L_tb) & " Input A2,A1,A0= " & to_bstring(A_tb) & " | Output Y7...Y0= " & to_bstring(Y_tb) & LF & " "; end loop; report "Simulation Complete."; wait; end process; end Behavior;