library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity full_adder_TB is

end full_adder_TB;

architecture Behavior of full_adder_TB is
   
    component full_adder
        Port ( A    : in STD_LOGIC;
               B    : in STD_LOGIC;
               Cin  : in STD_LOGIC;
               Sum  : out STD_LOGIC;
               Cout : out STD_LOGIC);
    end component;

    
    signal A, B, Cin : STD_LOGIC := '0';
    signal Sum, Cout : STD_LOGIC;

begin
 
    uut: full_adder port map (
        A => A, 
        B => B, 
        Cin => Cin, 
        Sum => Sum, 
        Cout => Cout
    );

  
    stim_proc: process
    begin
        --  0 + 0 + 0
        A <= '0'; B <= '0'; Cin <= '0'; wait for 10 ns;
        report "Inputs: A=" & std_logic'image(A) & " B=" & std_logic'image(B) & " Cin=" & std_logic'image(Cin) & 
               " | Outputs: Sum=" & std_logic'image(Sum) & " Cout=" & std_logic'image(Cout);

        -- 0 + 0 + 1
        A <= '0'; B <= '0'; Cin <= '1'; wait for 10 ns;
        report "Inputs: A=" & std_logic'image(A) & " B=" & std_logic'image(B) & " Cin=" & std_logic'image(Cin) & 
               " | Outputs: Sum=" & std_logic'image(Sum) & " Cout=" & std_logic'image(Cout);

        -- 0 + 1 + 0
        A <= '0'; B <= '1'; Cin <= '0'; wait for 10 ns;
        report "Inputs: A=" & std_logic'image(A) & " B=" & std_logic'image(B) & " Cin=" & std_logic'image(Cin) & 
               " | Outputs: Sum=" & std_logic'image(Sum) & " Cout=" & std_logic'image(Cout);

        -- 0 + 1 + 1
        A <= '0'; B <= '1'; Cin <= '1'; wait for 10 ns;
        report "Inputs: A=" & std_logic'image(A) & " B=" & std_logic'image(B) & " Cin=" & std_logic'image(Cin) & 
               " | Outputs: Sum=" & std_logic'image(Sum) & " Cout=" & std_logic'image(Cout);

        -- 1 + 0 + 0
        A <= '1'; B <= '0'; Cin <= '0'; wait for 10 ns;
        report "Inputs: A=" & std_logic'image(A) & " B=" & std_logic'image(B) & " Cin=" & std_logic'image(Cin) & 
               " | Outputs: Sum=" & std_logic'image(Sum) & " Cout=" & std_logic'image(Cout);

        -- 1 + 0 + 1
        A <= '1'; B <= '0'; Cin <= '1'; wait for 10 ns;
        report "Inputs: A=" & std_logic'image(A) & " B=" & std_logic'image(B) & " Cin=" & std_logic'image(Cin) & 
               " | Outputs: Sum=" & std_logic'image(Sum) & " Cout=" & std_logic'image(Cout);

        -- 1 + 1 + 0
        A <= '1'; B <= '1'; Cin <= '0'; wait for 10 ns;
        report "Inputs: A=" & std_logic'image(A) & " B=" & std_logic'image(B) & " Cin=" & std_logic'image(Cin) & 
               " | Outputs: Sum=" & std_logic'image(Sum) & " Cout=" & std_logic'image(Cout);

        -- 1 + 1 + 1
        A <= '1'; B <= '1'; Cin <= '1'; wait for 10 ns;
        report "Inputs: A=" & std_logic'image(A) & " B=" & std_logic'image(B) & " Cin=" & std_logic'image(Cin) & 
               " | Outputs: Sum=" & std_logic'image(Sum) & " Cout=" & std_logic'image(Cout);

        -- End the simulation
        wait;
    end process;
end Behavior;