library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity half_adder is
    Port (
        A     : in  STD_LOGIC;  -- First 1-bit input
        B     : in  STD_LOGIC;  -- Second 1-bit input
        Sum   : out STD_LOGIC;  -- 1-bit sum output
        Carry : out STD_LOGIC   -- 1-bit carry output
    );
end half_adder;


architecture Dataflow of half_adder is
begin

    Sum <= A xor B;
    Carry <= A and B;

end Dataflow;