library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity half_adderTB is

end half_adderTB;

architecture Behavioral of half_adderTB is

    component half_adder
        Port (
            A     : in  STD_LOGIC;
            B     : in  STD_LOGIC;
            Sum   : out STD_LOGIC;
            Carry : out STD_LOGIC
        );
    end component;

    signal tb_A     : STD_LOGIC := '0';
    signal tb_B     : STD_LOGIC := '0';
    signal tb_Sum   : STD_LOGIC;
    signal tb_Carry : STD_LOGIC;

begin

    UUT: half_adder port map (
        A     => tb_A,
        B     => tb_B,
        Sum   => tb_Sum,
        Carry => tb_Carry
    );

    stimulus_process: process
    begin 

        -- A = 0, B = 0
        -- Sum = 0, Carry = 0
        tb_A <= '0';
        tb_B <= '0';
        wait for 10 ns; 
	report "A = " & std_logic'image(tb_A) & "  B = " & std_logic'image(tb_B) & 
	"  carry = " & std_logic'image(tb_Carry) & "  sum = " & std_logic'image(tb_Sum) & LF & "  ";
	
        -- A = 0, B = 1
        -- Sum = 1, Carry = 0
        tb_A <= '0';
        tb_B <= '1';
        wait for 10 ns;
	report "A = " & std_logic'image(tb_A) & "  B = " & std_logic'image(tb_B) & 
	"  carry = " & std_logic'image(tb_Carry) & "  sum = " & std_logic'image(tb_Sum) & LF & "  ";
        
		-- A = 1, B = 0
        -- Sum = 1, Carry = 0
        tb_A <= '1';
        tb_B <= '0';
        wait for 10 ns;
	report "A = " & std_logic'image(tb_A) & "  B = " & std_logic'image(tb_B) & 
	"  carry = " & std_logic'image(tb_Carry) & "  sum = " & std_logic'image(tb_Sum) & LF & "  ";

        -- A = 1, B = 1
        -- Sum = 0, Carry = 1
        tb_A <= '1';
        tb_B <= '1';
        wait for 10 ns;
	report "A = " & std_logic'image(tb_A) & "  B = " & std_logic'image(tb_B) & 
	"  carry = " & std_logic'image(tb_Carry) & "  sum = " & std_logic'image(tb_Sum) & LF & "  ";

        wait;
    end process;

end Behavioral;