library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity jkflipflop is
    Port ( J      : in  STD_LOGIC;
           K      : in  STD_LOGIC;
           clk    : in  STD_LOGIC;
           rst_n  : in  STD_LOGIC;  -- Active-low reset
			  Q      : buffer STD_LOGIC;
           --Q      : out STD_LOGIC;
           Q_bar  : out STD_LOGIC);
end jkflipflop;

architecture Behavioral of jkflipflop is
    
begin
    process(clk, rst_n)
    begin
        if (rst_n = '0') then
            Q <= '0';                      
				
        
		  elsif falling_edge(clk) then          
            if (J = '0' and K = '0') then
                Q <= Q;    
					 
            elsif (J = '0' and K = '1') then
                Q <= '0';             
					 
            elsif (J = '1' and K = '0') then
                Q <= '1';           
					
            elsif (J = '1' and K = '1') then
                Q <= not Q; 
					 
            end if;
        end if;
    end process;

 
    Q_bar <= not Q;
	
    
end Behavioral;