library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity logicgates is
    Port ( 
        A      : in  STD_LOGIC;  -- Input A
        B      : in  STD_LOGIC;  -- Input B
        Y_AND  : out STD_LOGIC;  -- Output for AND gate
        Y_OR   : out STD_LOGIC;  -- Output for OR gate
        Y_NOT  : out STD_LOGIC;  -- Output for NOT gate (using input A)
        Y_NAND : out STD_LOGIC;  -- Output for NAND gate
        Y_NOR  : out STD_LOGIC;  -- Output for NOR gate
        Y_XOR  : out STD_LOGIC;  -- Output for XOR gate
        Y_XNOR : out STD_LOGIC   -- Output for XNOR gate
    );
end logicgates;

architecture Dataflow of logicgates is
begin

    Y_AND  <= A and B;   -- AND logic operation
    Y_OR   <= A or B;    -- OR logic operation
    Y_NOT  <= not A;     -- NOT logic operation (Inverts A)
    Y_NAND <= A nand B;  -- NAND logic operation
    Y_NOR  <= A nor B;   -- NOR logic operation
    Y_XOR  <= A xor B;   -- XOR logic operation
    Y_XNOR <= A xnor B;  -- XNOR logic operation

end Dataflow;