library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity logicgates_TB is
end logicgates_TB;

architecture Behavioral of logicgates_TB is

    component logicgates
        Port ( A : in  STD_LOGIC;
               B : in  STD_LOGIC;
               Y_AND, Y_OR, Y_NOT, Y_NAND, Y_NOR, Y_XOR, Y_XNOR : out STD_LOGIC);
    end component;

    signal sig_A : STD_LOGIC := '0';
    signal sig_B : STD_LOGIC := '0';
    signal out_AND, out_OR, out_NOT, out_NAND, out_NOR, out_XOR, out_XNOR : STD_LOGIC;

begin
    UUT: logicgates port map (
        A => sig_A,
        B => sig_B,
        Y_AND  => out_AND,
        Y_OR   => out_OR,
        Y_NOT  => out_NOT,
        Y_NAND => out_NAND,
        Y_NOR  => out_NOR,
        Y_XOR  => out_XOR,
        Y_XNOR => out_XNOR
    );

    stim_proc: process
    begin
       
       -- A = 0, B = 0
        sig_A <= '0'; sig_B <= '0';
        wait for 10 ns; 
        report "Input A=0, B=0 | AND=" & std_logic'image(out_AND) &
               " OR=" & std_logic'image(out_OR) &
               " NOT(A)=" & std_logic'image(out_NOT) &
               " NAND=" & std_logic'image(out_NAND) &
               " NOR=" & std_logic'image(out_NOR) &
               " XOR=" & std_logic'image(out_XOR) &
               " XNOR=" & std_logic'image(out_XNOR);

        -- A = 0, B = 1
        sig_A <= '0'; sig_B <= '1';
        wait for 10 ns;
        report "Input A=0, B=1 | AND=" & std_logic'image(out_AND) &
               " OR=" & std_logic'image(out_OR) &
               " NOT(A)=" & std_logic'image(out_NOT) &
               " NAND=" & std_logic'image(out_NAND) &
               " NOR=" & std_logic'image(out_NOR) &
               " XOR=" & std_logic'image(out_XOR) &
               " XNOR=" & std_logic'image(out_XNOR);

        -- A = 1, B = 0
        sig_A <= '1'; sig_B <= '0';
        wait for 10 ns;
        report "Input A=1, B=0 | AND=" & std_logic'image(out_AND) &
               " OR=" & std_logic'image(out_OR) &
               " NOT(A)=" & std_logic'image(out_NOT) &
               " NAND=" & std_logic'image(out_NAND) &
               " NOR=" & std_logic'image(out_NOR) &
               " XOR=" & std_logic'image(out_XOR) &
               " XNOR=" & std_logic'image(out_XNOR);

        -- A = 1, B = 1
        sig_A <= '1'; sig_B <= '1';
        wait for 10 ns;
        report "Input A=1, B=1 | AND=" & std_logic'image(out_AND) &
               " OR=" & std_logic'image(out_OR) &
               " NOT(A)=" & std_logic'image(out_NOT) &
               " NAND=" & std_logic'image(out_NAND) &
               " NOR=" & std_logic'image(out_NOR) &
               " XOR=" & std_logic'image(out_XOR) &
               " XNOR=" & std_logic'image(out_XNOR);
      
        wait;
    end process;

end Behavioral;