library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4x1 is
    Port ( A   : in  STD_LOGIC;
           B   : in  STD_LOGIC;
           C   : in  STD_LOGIC;
           D   : in  STD_LOGIC;
           SEL : in  STD_LOGIC_VECTOR(1 downto 0);
           Y   : out STD_LOGIC);
end mux4x1;


architecture Behavioral of mux4x1 is
begin
    
    with SEL select
        Y <= A when "00",
             B when "01",
             C when "10",
             D when "11",
             '0' when others; 
end Behavioral;