library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4x1_tb is

end mux4x1_tb;

architecture Behavioral of mux4x1_tb is

   
    component mux4x1
        Port ( A   : in  STD_LOGIC;
               B   : in  STD_LOGIC;
               C   : in  STD_LOGIC;
               D   : in  STD_LOGIC;
               SEL : in  STD_LOGIC_VECTOR(1 downto 0);
               Y   : out STD_LOGIC);
    end component;

  
    signal A_tb   : STD_LOGIC := '0';
    signal B_tb   : STD_LOGIC := '0';
    signal C_tb   : STD_LOGIC := '0';
    signal D_tb   : STD_LOGIC := '0';
    signal SEL_tb : STD_LOGIC_VECTOR(1 downto 0) := "00";
    signal Y_tb   : STD_LOGIC;

begin

    
    uut: mux4x1 port map (
          A => A_tb,
          B => B_tb,
          C => C_tb,
          D => D_tb,
          SEL => SEL_tb,
          Y => Y_tb
        );

    
    stim_proc: process
    begin
        
        A_tb <= '1';
        B_tb <= '0';
        C_tb <= '1';
        D_tb <= '0';
        
        
        SEL_tb <= "00";
        wait for 10 ns;
        report "SEL=00 | Expected Y=1 | Actual Y=" & std_logic'image(Y_tb);

        
        SEL_tb <= "01";
        wait for 10 ns;
        report "SEL=01 | Expected Y=0 | Actual Y=" & std_logic'image(Y_tb);

        
        SEL_tb <= "10";
        wait for 10 ns;
        report "SEL=10 | Expected Y=1 | Actual Y=" & std_logic'image(Y_tb);

        
        SEL_tb <= "11";
        wait for 10 ns;
        report "SEL=11 | Expected Y=0 | Actual Y=" & std_logic'image(Y_tb);

        -- End simulation safely
        wait;
    end process;

end Behavioral;